LPODIS=0, REGFPM=0, LPOSTAT=0, BIASEN=0, CLKBIASDIS=0
Regulator Status and Control Register
| BIASEN | Bias Enable Bit 0 (0): Biasing disabled, core logic can run in full performance 1 (1): Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see device level specification for details) |
| CLKBIASDIS | Clock Bias Disable Bit 0 (0): No effect 1 (1): In STOP or VLPS mode the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device) |
| REGFPM | Regulator in Full Performance Mode Status Bit 0 (0): Regulator is in low power mode or transition to/from 1 (1): Regulator is in full performance mode |
| LPOSTAT | LPO Status Bit 0 (0): Low power oscillator in low phase 1 (1): Low power oscillator in high phase |
| LPODIS | LPO Disable Bit 0 (0): Low power oscillator enabled 1 (1): Low power oscillator disabled |